Si4730/31-D50
Table 6. 3-Wire Control Interface Characteristics
(V A = 2.7 to 5.5 V, V D = 1.62 to 3.6 V, T A = –20 to 85 °C)
Parameter
SCLK Frequency
SCLK High Time
SCLK Low Time
SDIO Input, SEN to SCLK ?? Setup
SDIO Input to SCLK ?? Hold
SEN Input to SCLK ? ? Hold
SCLK ?? to SDIO Output Valid
SCLK ?? to SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall time
Symbol
f CLK
t HIGH
t LOW
t S
t HSDIO
t HSEN
t CDV
t CDZ
t R , t F
Test Condition
Read
Read
Min
0
25
25
20
10
10
2
2
Typ
Max
2.5
25
25
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK
70%
30%
t S
t R
t F
t HSDIO
t HIGH
t LOW
t HSEN
SEN
70%
30%
t S
SDIO
70%
30%
A7
A6-A5,
R/W,
A4-A1
A0
D15
D14-D1
D0
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
SCLK
70%
30%
SEN
SDIO
70%
30%
70%
30%
t S
A7
A6-A5,
R/W,
A4-A1
t S
t HSDIO
A0
t CDV
D15
D14-D1
t HSEN
D0
t CDZ
Address In
? Cycle Bus
Data Out
Turnaround
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
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